module bin2BCD_4dig(input clk, input [15:0] sw, output [6:0] seg, output [3:0] an, output dp);
    reg [3:0] bit_cnt, out3, out2, out1, out0; reg din, done;
    wire [3:0] dout,BCD3, BCD2, BCD1, BCD0; wire overflow;
    
    bin2BCD_1dig dig0 (.done(done), .d_in(din), .clk(clk), .d_out(dout[0]), .Q(BCD0));
    bin2BCD_1dig dig1 (.done(done), .d_in(din), .clk(clk), .d_out(dout[1]), .Q(BCD1));
    bin2BCD_1dig dig2 (.done(done), .d_in(din), .clk(clk), .d_out(dout[2]), .Q(BCD2));
    bin2BCD_1dig dig3 (.done(done), .d_in(din), .clk(clk), .d_out(dout[3]), .Q(BCD3));
    sseg_x4_top disp0 (.sw({out3, out2, out1, out0}), .dec_pnt(overflow), .seg(seg), .an(an), .dp(dp), .clk(clk));
    // An optional input to the 7-segment display may be added for an input to the decimal point to handle the overflow
    
    assign overflow = !(sw > 16'h270F);
    
    initial begin bit_cnt = 4'hF; {out3, out2, out1, out0} = 16'h0000; end
    always @ (posedge clk)begin bit_cnt = bit_cnt - 1; end
    always @ (posedge clk) begin  if (done) {out3, out2, out1, out0} <= {BCD3[2:0], BCD2[3:0], BCD1[3:0], BCD0[3:0], din}; end
    always @ (bit_cnt, sw) begin din = sw[bit_cnt]; done = (bit_cnt == 4'b0000); end
endmodule

module bin2BCD_1dig(input done, input d_in, input clk, output d_out, output reg [3:0] Q);
    parameter wait2strt = 2'b00; parameter shift = 2'b01; parameter add3_shift = 2'b10;
    
    reg [1:0] state, next_state; reg [3:0] D;
    wire [3:0] next_data, next_data3; wire GT4;
    
    assign GT4 = next_data > 4;
    assign next_data3 = next_data + 3;
    assign next_data = {Q[2:0], d_in};
    assign d_out = Q[3];
    
    always @ (state) case (state)
        wait2strt:  if (!done)              begin next_state = shift; D = next_data;   end
                    else                    begin next_state = wait2strt; D = 4'b0000; end
        shift:      if(GT4 && !done)        begin next_state = add3_shift; D = next_data3; end
                    else if (!GT4&& !done)  begin next_state = shift; D = next_data; end
                    else                    begin next_state = wait2strt; D = 4'b0000; end
        add3_shift: if (GT4 && !done)       begin next_state = add3_shift; D = next_data3; end
                    else if (!GT4 && !done) begin next_state = shift; D = next_data; end
                    else                    begin next_state = wait2strt; D = 4'b0000; end endcase
    
    initial begin state = 2'b00; Q = 4'b0000; end
    always @ (posedge clk) state <= next_state;
    always @ (posedge clk) Q <= D;
endmodule

module sseg_x4_top(input clk, rst, dec_pnt, input [15:0] sw, output [6:0] seg, output [3:0] an, output dp);
    wire clkd; wire [3:0] hex_num;  
    sseg_display U0(.seg(seg), .sw(hex_num));
    clk_gen U1(clk, rst, clkd);
    digit_selector U2(clkd, rst, an);
    hex_num_gen U3(an, sw, hex_num);
    assign dp = dec_pnt ? 1'b0 : 1'b1;
endmodule

module clk_gen(input clk, rst, output clk_div);
    reg [26:0] counter; assign clk_div = counter[18]; //use bit 2 for sim then 18 for implementation
    
    initial begin counter <= 27'b000000000000000000000000000; end
    
    always @ (posedge clk, posedge rst) begin
        if (rst)      counter <= 27'b000000000000000000000000000;
        else          counter <= counter + 1'b1; end
endmodule

module sseg_display(input [3:0] sw, output dp, output [3:0] an, output reg [6:0] seg );
    assign an = 4'b1110; assign dp = 1'b1; initial seg = 7'b1000000;
    
    always @(sw)  begin
        if      (sw == 4'b0000) seg = 7'b1000000; // 0
        else if (sw == 4'b0001) seg = 7'b1111001; // 1
        else if (sw == 4'b0010) seg = 7'b0100100; // 2
        else if (sw == 4'b0011) seg = 7'b0110000; // 3
        else if (sw == 4'b0100) seg = 7'b0011001; // 4
        else if (sw == 4'b0101) seg = 7'b0010010; // 5
        else if (sw == 4'b0110) seg = 7'b0000010; // 6
        else if (sw == 4'b0111) seg = 7'b1111000; // 7
        else if (sw == 4'b1000) seg = 7'b0000000; // 8 
        else if (sw == 4'b1001) seg = 7'b0010000; // 9
        else if (sw == 4'b1010) seg = 7'b0001000; // A
        else if (sw == 4'b1011) seg = 7'b0000011; // B
        else if (sw == 4'b1100) seg = 7'b1000110; // C
        else if (sw == 4'b1101) seg = 7'b0100001; // D
        else if (sw == 4'b1110) seg = 7'b0000110; // E
        else if (sw == 4'b1111) seg = 7'b0001110; // F
        else seg = 7'bXXXXXXX; end  //don't care for simulation
endmodule

module digit_selector(input clk, rst, output reg [3:0] digit_sel);
    initial begin digit_sel <= 4'b1110; end
    
    always@(posedge clk, posedge rst) begin
            if (rst) digit_sel <= 4'b1110;
            else begin 
            digit_sel[3:1] <= digit_sel[2:0];
            digit_sel[0]   <= digit_sel[3]; end end    
endmodule

module hex_num_gen(input [3:0] digit_sel, input [15:0] sw, output reg [3:0] hex_num);
    always@ * begin
        if      (digit_sel == 4'b1110) hex_num = sw[3:0];
        else if (digit_sel == 4'b1101) hex_num = sw[7:4];
        else if (digit_sel == 4'b1011) hex_num = sw[11:8];
        else if (digit_sel == 4'b0111) hex_num = sw[15:12];
        else hex_num = 4'bxxxx; end
endmodule