`timescale 1ns / 1ps

module decoder(input A, B, C, output led0, led1, led2, led3, led4, led5, led6, led7);
    wire a, b, c;
    
    not Not0(a, A);
    not Not1(b, B);
    not Not2(c, C);
    
    and AND0(led0, a, b, c);
    and AND1(led1, a, b, C);
    and AND2(led2, a, B, c);
    and AND3(led3, a, B, C);
    and AND4(led4, A, b, c);
    and AND5(led5, A, b, C);
    and AND6(led6, A, B, c);
    and AND7(led7, A, B, C);  
          
endmodule