Hierarchical design of digital systems. Circuit synthesis and simulation using the Verilog hardware description language. Circuit implementation with field programmable gate arrays (FPGAs). Technical reports and presentations are required. Laboratory exercises are included.
ECEN 160, ECEN 160L, ECEN 260
Office Phone: 208-496-7626
Office: STC320V
Office Hours:
M-F - 11:45AM - 12:45PM
(Or by appointment)
At the conclusion of this course you should be able to:
1. Develop and evaluate complex combinational and sequential circuits.
2. Describe digital systems in Verilog HDL.
3. Simulate and debug Verilog-based digital systems.
4. Synthesize Verilog designs and evaluate using the ARTIX 7 FPGA.
5. Analyze timing of digital systems.
Homework will generally be assigned weekly.
After the initial week of class, lab projects will be a major emphasis in the course to solidify your understanding of Verilog-based Digital System Design. Labs will be graded on both functionality (50%) and lab report content (50%).
Late assignments and labs will be subject a penalty of 10% per day up to 50% of the possible points. There will be no points awarded if the assignment or lab is more than two weeks late. If there is a true emergency, let’s talk.
There will be regular in-class quizzes on the assigned preparation materials.
| Reading Preparation and Attendance | 10% |
| Homework | 20% |
| Lab Projects | 30% |
| Midterm Exam | 15% |
| Final Exam | 15% |
| Project | 10% |
| Total | 100% |
| Standard BYU-Idaho Grading Scale | |||||||
| 94-100% | A | 90-92.9% | A- | 87-89.9% | B+ | ||
| 83-86.9% | B | 80-82.9% | B- | 77-79.9% | C+ | ||
| 73-76.9% | C | 70-72.9% | C- | 67-69.9% | D+ | ||
| 63-66.9% | D | 60-62.9% | D- | Below 60% | F | ||
| Date | Details |
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