Write a Verilog module to interface to one digit of the 7-seg display. You will use four of the switches to control the displayed value. You will use the “if, else if, else” structure to interface to display. From the constraints file, you will be using “an”, “dp”, “seg”, and “sw”.
Synthesize the design and fix all errors. Run simulation (behavioral). Observe the value of sw[3:0] (Figure 1). Right click on “value” and select “Force Constant” to for sw[3:0] to 0 (Figure 2). Above the waveform viewer, you will see two blue run arrows. To run the simulation for 1us, enter 1us in the box to the right of the blue arrows, select the blue arrow with the “t”, and observe the simulated contents of sseg (Figure 3). Change the forced value of “sw” to simulate each of the possibilities for to verify functionality. After each simulation, you will need to “right click” on the simulation output window to resize the simulation viewing area. Generate Bitstream and program device to verify the actual functionality of your design.
Write a test bench to simulate all of the possible switch settings.
Here's the Lab Code. Lab 3 Code
Here's the Lab Test Bench. Lab 3 TB