Lab Requirements

After the initial week of class, lab projects will be a major emphasis in the course to solidify your understanding of Verilog-based Digital System Design. Labs will be graded on both functionality (50%) and lab report content (50%). Lab Functionality – Labs must be fully functional and on time for full credit. Lab Report Content – Please submit well-documented Verilog code and applicable design notes for full credit. You will need to carefully follow the instructions provided for each lab. Late assignments and labs will be subject a penalty of 10% per day up to 50% of the possible points. There will be no points awarded if the assignment or lab is more than two weeks late. If there is a true emergency, let’s talk.

Lab Materials

• "Fundamentals of Digital Logic with Verilog Design", by Stephen Brown and Zvonko Vranesic
• Optional hardware: Basys 3 FPGA Board

Optional software:

• EVITA Verilog Tutorial
• Vivado Design Design Suite (The "WebPack" license is free of charge.) Vivado Installation Tutorial
• Standard campus plug-ins for your browser