Overview

The objective of this lab is to evaluate the timing of Lab 5’s memory design to determine it’s maximum operating frequency for:

1. An 8-bit adder using the “+” operator
2. An 8-bit multiplier using the “*” operator
3. An 8-bit multiplier using the instantiation of Lab 2, the continuous assignment (data-flow) multiplier.

In other words, for part B, you will replace the “+” operator in lab 5 with an instantiation of your Lab 2 multiplier in order to evaluate its maximum speed. For part C, you must write a new and improved multiplier module. The final objective of this lab is to speed up the clock rate of the multiplier by pipelining the design. Increased slack by 10x the original value. So the speed of running was 10x less. Pipelining was a way to optimize code and hardware.

Here's the Lab Code. Memory Code (Lab 5)   Pipelined (Multiplier Lab2)

Here's the Lab Test Bench. Lab 6 TB